EP7312_05 Datasheet, PDF (52/64 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced

EP7312
High-Performance, Low-Power System on Chip
Ball Location
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
Name
CTS
VSSRTC
VSSRTC
A[17]/DRA[10]
A[16]/DRA[11]
A[15]/DRA[12]
A[14]/DRA[13]
nTRST
D[16]
D[17]
LEDDRV
PHDIN
VSSIO
DCD
nTEST[1]
EINT[3]
VSSRTC
ADCIN
COL[4]
TCLK
D[20]
D[19]
D[18]
VSSIO
VDDIO
VDDIO
RXD[1]
DSR
VDDIO
nEINT[1]
PE[2]/CLKSEL
VSSRTC
PD[0]/LEDFLSH
VSSRTC
COL[6]
D[31]
VSSRTC
A[22]/DRA[5]
A[21]/DRA[6]
VSSIO
A[18]/DRA[9]
A[19]/DRA[8]
nTEST[0]
nEINT[2]
VDDIO
PE[0]/BOOTSEL[0]
TMS
Table 22. 256-Ball PBGA Ball Listing (Continued)
Strength^†
Reset
State
1
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
Low
With p/u*
1
High
1
Low
1
Low
1
Low
1
‡
Input
1
Low
1
High
1
Low
1
Low
1
Low
1
Low
1
Low
With p/u*
1
with p/u*
‡
Input
Type
I
RTC ground
RTC ground
O
O
O
O
I
I/O
I/O
O
I
Pad ground
I
I
I
RTC ground
I
O
I
I/O
I/O
I/O
Pad ground
Pad power
Pad power
I
I
Pad power
I
I/O
RTC ground
I/O
Core ground
O
I/O
RTC ground
O
O
Pad ground
O
O
I
I
Pad power
I
I
Description
UART 1 clear to send input
Real time clock ground
Real time clock ground
System byte address / SDRAM address
System byte address / SDRAM address
System byte address / SDRAM address
System byte address / SDRAM address
JTAG async reset input
Data I/O
Data I/O
IR LED drive
Photodiode input
I/O ground
UART 1 data carrier detect
Test mode select input
External interrupt
Real time clock ground
SSI1 ADC serial input
Keyboard scanner column drive
JTAG clock
Data I/O
Data I/O
Data I/O
I/O ground
Digital I/O power, 3.3V
Digital I/O power, 3.3V
UART 1 receive data input
UART 1 data set ready input
Digital I/O power, 3.3V
External interrupt input
GPIO port E / clock input mode select
Real time clock ground
GPIO port D / LED blinker output
Real time clock ground
Keyboard scanner column drive
Data I/O
Real time clock ground
System byte address / SDRAM address
System byte address / SDRAM address
I/O ground
System byte address / SDRAM address
System byte address / SDRAM address
Test mode select input
External interrupt input
Digital I/O power, 3.3V
GPIO port E / Boot mode select
JTAG mode select
52
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(All Rights Reserved)
DS508F1