EP7312_05 Datasheet, PDF (40/64 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced

EP7312
High-Performance, Low-Power System on Chip
204-Ball TFBGA Ball Listing
The list is ordered by ball location.
Table 21. 204-Ball TFBGA Ball Listing
Ball Location
Name
A1
VDDIO
A2
EXPCLK
A3
nCS[3]
A4
nCS[1]
A5
nMWE/nSDWE
A6
SDQM[2]
A7
nSDCS[1]
A8
DD[2]
A9
FRM
A10
CL[1]
A11
VSSCORE
A12
D[1]
A13
A[2]
A14
D[4]
A15
A[5]
A16
nPWRFL
A17
MOSCOUT
A18
VSSIO
A19
VSSIO
A20
VSSIO
B1
WORD
B2
VDDIO
B3
nCS[5]
B4
nCS[2]
B5
nMOE/nSDCAS
B6
SDCKE
B7
nSDCS[0]
B8
DD[1]
B9
M
B10
CL[2]
B11
D[0]
B12
A[1]
B13
D[3]
†
Strength
Reset
State
1
1
High
1
High
1
High
2
Low
1
High
1
Low
1
Low
1
Low
1
Low
2
Low
1
Low
1
Low
1
Low
1
Low
1
High
1
High
2
Low
1
High
1
Low
1
Low
1
Low
1
Low
2
Low
2
Low
Type
Pad power
I
O
O
O
O
O
O
O
O
Core ground
I/O
O
I/O
O
I
O
Pad ground
Pad ground
Pad ground
O
Pad power
O
O
O
O
O
O
O
0
I/O
O
I/O
Description
Digital I/O power,
3.3 V
Expansion clock input
Chip select 3
Chip select 1
ROM, expansion write enable/ SDRAM write enable control signal
SDRAM byte lane mask
SDRAM chip select 2
LCD serial display data
LCD frame synchronization pulse
LCD line clock
Core ground
Data I/O
System byte address
Data I/O
System byte address
Power fail sense input
Main oscillator out
I/O ground
I/O ground
I/O ground
Word access select output
Digital I/O power, 3.3 V
Chip select 5
Chip select 2
ROM, expansion OP enable/SDRAM CAS control signal
SDRAM clock enable output
SDRAM chip select 0
LCD serial display data
LCD AC bias drive
LCD pixel clock out
Data I/O
System byte address
Data I/O
40
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(All Rights Reserved)
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