EP7312_05 Datasheet, PDF (54/64 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced

EP7312
High-Performance, Low-Power System on Chip
Ball Location
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
Name
SSITXDA
nADCCS
VDDIO
ADCOUT
COL[7]
COL[3]
COL[1]
D[30]
A[27]/DRA[0]
A[25]/DRA[2]
VDDIO
A[24]/DRA[3]
VDDRTC
PD[7]/SDQM[1]
PD[6]/SDQM[0]
PD[3]
SSICLK
SSIRXFR
VDDCORE
DRIVE[0]
FB[1]
COL[5]
VDDIO
BUZ
D[28]
A[26]/DRA[1]
D[25]
VSSIO
Table 22. 256-Ball PBGA Ball Listing (Continued)
Strength^†
1
1
Reset
State
Low
High
1
Low
1
High
1
High
1
High
1
Low
2
Low
2
Low
1
Low
1
Low
1
Low
1
Low
1
Input^‡
1
Input^‡
2
High /
Low
1
High
1
Low
1
Low
2
Low
1
Low
Type
O
O
Pad power
O
O
O
O
I/O
O
O
Pad power
O
RTC power
I/O
I/O
I/O
I/O
I/O
Core power
I/O
I
O
Pad power
O
I/O
O
I/O
Pad ground
Description
DAI/CODEC/SSI2 serial data output
SSI1 ADC chip select
Digital I/O power, 3.3V
SSI1 ADC serial data output
Keyboard scanner column drive
Keyboard scanner column drive
Keyboard scanner column drive
Data I/O
System byte address / SDRAM address
System byte address / SDRAM address
Digital I/O power, 3.3V
System byte address / SDRAM address
Real time clock power, 2.5V
GPIO port D / SDRAM byte lane mask
GPIO port D / SDRAM byte lane mask
GPIO port D
DAI/CODEC/SSI2 serial clock
DAI/CODEC/SSI2 frame sync
Core power, 2.5V
PWM drive output
PWM feedback input
Keyboard scanner column drive
Digital I/O power, 3.3V
Buzzer drive output
Data I/O
System byte address / SDRAM address
Data I/O
I/O ground
*“With _{p/u” means with internal pull-up of 100 KOhms on the pin.}
† _{Strength 1 = 4 ma}
Strength 2 = 12 ma
‡_{Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.}
JTAG Boundary Scan Signal Ordering
Table 23. JTAG Boundary Scan Signal Ordering
LQFP TFBGA PBGA
Pin No. Ball
Ball
Signal
Type
1
B3
B1
nCS[5]
O
4
A2
C2
EXPCLK
I/O
5
B1
E4
WORD
O
6
E3
D1
WRITE/nSDRAS
O
7
C1
F5
RUN/CLKEN
O
Position
1
3
6
8
10
54
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(All Rights Reserved)
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