EP7312_05 Datasheet, PDF (16/64 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced

EP7312
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for
the timings of each of the SDRAM modes.
Parameter
SDCLK falling edge to SDCS assert delay time
SDCLK falling edge to SDCS deassert delay time
SDCLK falling edge to SDRAS assert delay time
SDCLK falling edge to SDRAS deassert delay time
SDCLK falling edge to SDRAS invalid delay time
SDCLK falling edge to SDCAS assert delay time
SDCLK falling edge to SDCAS deassert delay time
SDCLK falling edge to ADDR transition time
SDCLK falling edge to ADDR invalid delay time
SDCLK falling edge to SDMWE assert delay time
SDCLK falling edge to SDMWE deassert delay time
DATA transition to SDCLK falling edge time
SDCLK falling edge to DATA transition hold time
SDCLK falling edge to DATA transition delay time
Symbol
t_CSa
t_CSd
t_RAa
t_RAd
t_RAnv
t_CAa
t_CAd
t_ADv
t_ADx
t_MWa
t_MWd
t_DAs
t_DAh
t_DAd
Min
0
−3
1
−3
2
−2
−5
−3
−2
−3
−4
2
1
0
Typ
2
2
3
1
4
2
0
1
2
1
0
-
-
-
Max
4
10
7
10
7
5
3
5
5
5
4
-
-
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
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