SAMA5D42_14 Datasheet, PDF (692/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

32.7.13 LCD Controller Interrupt Mask Register
Name:
LCDC_LCDIMR
Address: 0xF0000034
Access:
Read-only
31
30
29
28
–
–
–
–
23
22
21
20
–
–
–
–
15
14
13
12
–
–
–
–
7
6
5
4
–
–
–
FIFOERRIM
27
–
19
–
11
HEOIM
3
–
26
–
18
–
10
OVR2IM
2
DISPIM
• SOFIM: Start of Frame Interrupt Mask Register
0: Interrupt source is disabled
1: Interrupt source is enabled
• DISIM: LCD Disable Interrupt Mask Register
0: Interrupt source is disabled
1: Interrupt source is enabled
• DISPIM: Power UP/Down Sequence Terminated Interrupt Mask Register
0: Interrupt source is disabled
1: Interrupt source is enabled
• FIFOERRIM: Output FIFO Error Interrupt Mask Register
0: Interrupt source is disabled
1: Interrupt source is enabled
• BASEIM: Base Layer Interrupt Mask Register
0: Interrupt source is disabled
1: Interrupt source is enabled
• OVR1IM: Overlay 1 Interrupt Mask Register
0: Interrupt source is disabled
1: Interrupt source is enabled
• OVR2IM: Overlay 2 Interrupt Mask Register
0: Interrupt source is disabled
1: Interrupt source is enabled
• HEOIM: High End Overlay Interrupt Mask Register
0: Interrupt source is disabled
1: Interrupt source is enabled
25
–
17
–
9
OVR1IM
1
DISIM
24
–
16
–
8
BASEIM
0
SOFIM
692
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14