SAMA5D42_14 Datasheet, PDF (1590/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Table 50-2. Authorized Input Data Registers
Operation Mode
Input Data Registers to Write
8-bit CFB
AES_IDATAR0
CTR
All
GCM
All
Note: In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in processing.
Note: In 32, 16, and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 is not allowed and may
lead to errors in processing.
 Set the START bit in the AES Control Register (AES_CR) to begin the encryption or the decryption process.
 When processing completes, the DATRDY flag in the AES Interrupt Status Register (AES_ISR) is raised. If
an interrupt has been enabled by setting the DATRDY bit in the AES_IER, the interrupt line of the AES is
activated.
 When software reads one of the AES_ODATARx, the DATRDY bit is automatically cleared.
50.4.3.2 Auto Mode
The Auto Mode is similar to the manual one, except that in this mode, as soon as the correct number of
AES_IDATARx is written, processing is automatically started without any action in the AES_CR.
50.4.3.3 DMA Mode
The DMA Controller can be used in association with the AES to perform an encryption/decryption of a buffer
without any action by software during processing.
The SMOD field in the AES_MR must be configured to 0x2 and the DMA must be configured with non-incremental
addresses.
The start address of any transfer descriptor must be configured with the address of AES_IDATAR0.
The DMA chunk size configuration depends on the AES mode of operation and is listed in Table 50-3 “DMA Data
Transfer Type for the Different Operation Modes”.
When writing data to AES with a first DMA channel, data are first fetched from a memory buffer (source data). It is
recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the
destination data size depends on the mode of operation. When reading data from the AES with the second DMA
channel, the source data is the data read from AES and data destination is the memory buffer. In this case, the
source data size depends on the AES mode of operation and is listed in Table 50-3.
Table 50-3. DMA Data Transfer Type for the Different Operation Modes
Operation Mode
Chunk Size
Destination/Source Data Transfer Type
ECB
4
Word
CBC
4
Word
OFB
4
Word
CFB 128-bit
4
Word
CFB 64-bit
1
Word
CFB 32-bit
1
Word
CFB 16-bit
1
Half-word
CFB 8-bit
1
Byte
CTR
4
Word
GCM
4
Word
1590
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14