SAMA5D42_14 Datasheet, PDF (1204/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Reversal of Write to Read
The master initiates the communication by a write command and finishes it by a read command.
Figure 40-31 describes the repeated start + reversal from write to read mode.
Figure 40-31. Repeated Start + Reversal from Write to Read Mode
TWI_THR
DATA2
DATA3
TWD
S SADR W A DATA0 A DATA1 A Sr SADR R A DATA2 A DATA3 NA P
TWI_RHR
SVACC
SVREAD
TXRDY
RXRDY
EOSACC
TXCOMP
DATA0
Read TWI_RHR
As soon as a START is detected
DATA1
Cleared after read
Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before
the ACK.
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
40.7.5.6 Using the DMA Controller
The use of the DMA significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequence.
Data Transmit with the DMA
1. Initialize the DMA (channels, memory pointers, size, etc.).
2. Configure the slave mode.
3. Enable the DMA.
4. Wait for the DMA BTC flag.
5. Disable the DMA.
6. (Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.
Data Receive with the DMA
The DMA transfer size must be defined with the buffer size. In slave mode, the number of characters to receive
must be known in order to configure the DMA.
1. Initialize the DMA (channels, memory pointers, size, etc.).
2. Configure the slave mode.
3. Enable the DMA.
4. Wait for the DMA BTC flag.
5. Disable the DMA.
6. (Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.
1204
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14