SAMA5D42_14 Datasheet, PDF (1579/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

49.4 Product Dependencies
49.4.1 Power Management
The TRNG interface may be clocked through the Power Management Controller (PMC), thus the programmer
must first configure the PMC to enable the TRNG user interface clock. The user interface clock is independent
from any clock that may be used in the entropy source logic circuitry. The source of entropy can be enabled before
enabling the user interface clock.
49.4.2 Interrupt
The TRNG interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the
Interrupt Controller must be programmed before configuring the TRNG.
Table 49-1. Peripheral IDs
Instance
ID
TRNG
53
49.5
Functional Description
As soon as the TRNG is enabled in the control register (TRNG_CR), the generator provides one 32-bit value every
84 clock cycles. Interrupt trng_int can be enabled in the TRNG_IER (respectively disabled in the TRNG_IDR). This
interrupt is set when a new random value is available and is cleared when the status register (TRNG_ISR) is read.
The flag DATRDY of the (TRNG_ISR) is set when the random data is ready to be read out on the 32-bit output
data register (TRNG_ODATA).
The normal mode of operation checks that the status register flag equals 1 before reading the output data register
when a 32-bit random value is required by the software application.
Figure 49-2. TRNG Data Generation Sequence
Clock
trng_cr
enable
trng_int
84 clock cycles
84 clock cycles
Read TRNG_ISR
Read TRNG_ODATA
84 clock cycles
Read TRNG_ISR
Read TRNG_ODATA
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
1579