SAMA5D42_14 Datasheet, PDF (513/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

30.17.3 NFC Initialization
Prior to any Command and Data Transfer, the SMC User Interface must be configured to meet the device timing
requirements.
 Write enable Configuration
Use NWE_SETUP, NWE_PULSE and NWE_CYCLE to define the write enable waveform according to the
external device datasheet.
Use TADL field in the HSMC_TIMINGS register to configure the timing between the last address latch cycle and
the first rising edge of WEN for data input.
Figure 30-32. Write Enable Timing Configuration
mck
wen
t _{WEN_SETUP}
t _{WEN_PULSE}
t _{WEN_HOLD}
t _{WEN_CYCLES}
Figure 30-33. Write Enable Timing for NAND Flash Device Data Input Mode
mck
ale
wen
t _ADL
 Read Enable Configuration
Use NRD_SETUP, NRD_PULSE and NRD_CYCLE to define the read enable waveform according to the external
device datasheet.
Use TAR field in the HSMC_TIMINGS register to configure the timings between the address latch enable falling
edge to read the enable falling edge.
Use TCLR field in the HSMC_TIMINGS register to configure the timings between the command latch enable falling
edge to read the enable falling edge.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
513