SAMA5D42_14 Datasheet, PDF (32/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

6.1 Embedded Memory
6.1.1
Scrambled Internal SRAM
The SAMA5D4 product embeds a total of 128 Kbytes of scrambled high-speed SRAM. After reset and until the
Remap command is performed, SRAM is accessible at the address: 0x0020 0000. After remap of AXI Bus Matrix,
SRAM is also available at the address 0x0.
6.1.2
Secured Backup SRAM
The device embeds secure memories (8 Kbytes of SRAM) which are dedicated to the storage of sensitive data.
The secure backup SRAM is described in the document “Secure Box Module (SBM)”, Atmel literature No. 11254.
This document is available under Non-Disclosure Agreement (NDA). Contact an Atmel Sales Representative for
further details.
6.1.3
Scrambled Internal ROM
The product embeds one 128-Kbyte secured scrambled internal ROM mapped at address 0 after reset. The ROM
contains a standard and a secure bootloader as well as the BCH (Bose, Chaudhuri and Hocquenghem) code
tables for NAND Flash ECC correction.
The standard bootloader supports booting from:
 8-bit NAND Flash with ECC management
 SPI Serial Flash
 SDCARD
 EMMC
 TWI EEPROM
The boot sequence can be selected using the boot order facility (Boot Select Control Register). The internal ROM
embeds Galois field tables that are used to compute NAND Flash ECC. Refer to Figure 13-9 “Galois Field Table
Mapping” in Section 13. “Standard Boot Strategies” of this datasheet.
6.1.4
Boot Strategies
For standard boot strategies, refer to Section 13. “Standard Boot Strategies” of this datasheet.
For secure boot strategies, refer to the application note “SAMA5D4x Secure Boot Strategy”, Atmel literature No.
11295 (NDA required).
32 SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14