SAMA5D42_14 Datasheet, PDF (1677/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

54.4.2 Interrupt
The ICM interface has an interrupt line connected to the Interrupt Controller.
Handling the ICM interrupt requires programming the interrupt controller before configuring the ICM.
Table 54-1. Peripheral IDs
Instance
ID
ICM
9
54.5
Functional Description
The Integrity Check Monitor (ICM) is a DMA controller that performs SHA-based memory hashing over memory
regions. As shown in Figure 54-2, it integrates a DMA interface, a Monitoring Finite State Machine (FSM), an
integrity scheduler, a set of context registers, a SHA engine, an APB interface and configuration registers.
When the ICM module is enabled, it sequentially retrieves a circular list of region descriptors from the memory
(Main List described in Figure 54-3). Up to four regions may be monitored. Each region descriptor is composed of
four words indicating the layout of the memory region (see Figure 54-4). It also contains the hashing engine
configuration on a per region basis. As soon as the descriptor is loaded from the memory and context registers are
updated with the data structure, the hashing operation starts. A programmable number of blocks (see TRSIZE field
of the ICM_RCTRL structure member) is transferred from the memory to the SHA engine. When the desired
number of blocks have been transferred, the digest is whether moved to memory (Write Back function) or
compared with a digest reference located in the system memory (Compare function). If a digest mismatch occurs,
an interrupt is triggered if unmasked. The ICM module passes through the region descriptor list until the end of the
list marked by an End of List bit set to one. To continuously monitor the list of regions, the WRAP bit must be set to
one in the last data structure.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
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