SAMA5D42_14 Datasheet, PDF (1159/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Figure 39-9. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
SPCK
MISO
MOSI
SPI Master
NPCS0
NPCS1
NPCS2
NPCS3
SPCK MISO MOSI SPCK MISO MOSI
Slave 0
Slave 1
NSS
NSS
SPCK MISO MOSI
Slave 14
NSS
Decoded chip select lines
External 1-of-n Decoder/Demultiplexer
39.7.3.8 Peripheral Deselection without DMA
During a transfer of more than one unit of data on a Chip Select without the DMA, the SPI_TDR is loaded by the
processor, the TDRE flag rises as soon as the content of the SPI_TDR is transferred into the internal Shift register.
When this flag is detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the
end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the
Chip Select is not de-asserted between the two transfers. But depending on the application software handling the
SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor
may not reload the SPI_TDR in time to keep the chip select active (low). A null DLYBCT value (delay between
consecutive transfers) in the SPI_CSR, gives even less time for the processor to reload the SPI_TDR. With some
SPI slave peripherals, if the chip select line must remain active (low) during a full set of transfers, communication
errors can occur.
To facilitate interfacing with such devices, the Chip Select registers [CSR0...CSR3] can be programmed with the
Chip Select Active After Transfer (CSAAT) bit to 1. This allows the chip select lines to remain in their current state
(low = active) until a transfer to another chip select is required. Even if the SPI_TDR is not reloaded, the chip select
remains active. To de-assert the chip select line at the end of the transfer, the Last Transfer (LASTXFER) bit in the
SPI_MR must be set to 1 before writing the last data to transmit into the SPI_TDR.
39.7.3.9 Peripheral Deselection with DMA
DMA provides faster reloads of the SPI_TDR compared to software. However, depending on the system activity, it
is not guaranteed that the SPI_TDR is written with the next data before the end of the current transfer.
Consequently, data can be lost by the de-assertion of the NPCS line for SPI slave peripherals requiring the chip
select line to remain active between two transfers. The only way to guarantee a safe transfer in this case is the use
of the CSAAT and LASTXFER bits.
When the CSAAT bit is configured to 0, the NPCS does not rise in all cases between two transfers on the same
peripheral. During a transfer on a Chip Select, the TDRE flag rises as soon as the content of the SPI_TDR is
transferred into the internal shift register. When this flag is detected, the SPI_TDR can be reloaded. If this reload
occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the
current transfer, the Chip Select is not de-asserted between the two transfers. This can lead to difficulties to
interface with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
1159