SAMA5D42_14 Datasheet, PDF (629/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

31.9.28 XDMAC Channel x [x = 0..15] Configuration Register
Name:
XDMAC_CCx[x = 0..15]
Address: 0xF0004078 (1)[0], 0xF00040B8 (1)[1], 0xF00040F8 (1)[2], 0xF0004138 (1)[3], 0xF0004178 (1)[4],
0xF00041B8 (1)[5], 0xF00041F8 (1)[6], 0xF0004238 (1)[7], 0xF0004278 (1)[8], 0xF00042B8 (1)[9], 0xF00042F8 (1)[10],
0xF0004338 (1)[11], 0xF0004378 (1)[12], 0xF00043B8 (1)[13], 0xF00043F8 (1)[14], 0xF0004438 (1)[15], 0xF0014078
(0)[0], 0xF00140B8 (0)[1], 0xF00140F8 (0)[2], 0xF0014138 (0)[3], 0xF0014178 (0)[4], 0xF00141B8 (0)[5], 0xF00141F8
(0)[6], 0xF0014238 (0)[7], 0xF0014278 (0)[8], 0xF00142B8 (0)[9], 0xF00142F8 (0)[10], 0xF0014338 (0)[11], 0xF0014378
(0)[12], 0xF00143B8 (0)[13], 0xF00143F8 (0)[14], 0xF0014438 (0)[15]
Access:
Read/Write
31
30
29
28
27
26
25
24
–
PERID
23
22
21
20
WRIP
RDIP
INITD
–
19
18
DAM
17
16
SAM
15
14
13
12
11
–
DIF
SIF
DWIDTH
10
9
8
CSIZE
7
6
5
4
3
MEMSET
SWREQ
PROT
DSYNC
–
2
1
MBSIZE
0
TYPE
• TYPE: Channel x Transfer Type
0 (MEM_TRAN): Self triggered mode (Memory to Memory Transfer).
1 (PER_TRAN): Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).
• MBSIZE: Channel x Memory Burst Size
Value Name
Description
00
SINGLE
The memory burst size is set to one.
01
FOUR
The memory burst size is set to four.
10
EIGHT
The memory burst size is set to eight.
11
SIXTEEN
The memory burst size is set to sixteen.
• DSYNC: Channel x Synchronization
0 (PER2MEM): Peripheral to Memory transfer
1 (MEM2PER): Memory to Peripheral transfer
• PROT: Channel x Protection
0 (SEC): Channel is secured
1 (UNSEC): Channel is unsecured
• SWREQ: Channel x Software Request Trigger
0 (HWR_CONNECTED): Hardware request line is connected to the peripheral request line.
1 (SWR_CONNECTED): Software request is connected to the peripheral request line.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
629