SAMA5D42_14 Datasheet, PDF (176/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

18.2
Embedded Characteristics
 Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM^® Processor
 128 Individually Maskable and Vectored Interrupt Sources
̶ Source 0 is Reserved for the Fast Interrupt Input (FIQ)
̶ Source 1 is Reserved for System Peripheral Interrupts
̶ Source 2 to Source 127, Control up to 126 Embedded Peripheral Interrupts or External Interrupts
̶ Programmable Edge-triggered or Level-sensitive Internal Sources
̶ Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources
 8-level Priority Controller
̶ Drives the Normal Interrupt of the Processor
̶ Handles Priority of the Interrupt Sources 1 to 127
̶ Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt
 Vectoring
̶ Optimizes Interrupt Service Routine Branch and Execution
̶ One 32-bit Vector Register for all Interrupt Sources
̶ Interrupt Vector Register Reads the Corresponding Current Interrupt Vector
 Protect Mode
̶ Easy Debugging by Preventing Automatic Operations when Protect Models are Enabled
 General Interrupt Mask
̶ Provides Processor Synchronization on Events Without Triggering an Interrupt
 Register Write Protection
 AIC0 is Non Secure AIC, AIC1 is Secure AIC
 AIC0 manages nIRQ line, AIC1 manages nFIQ line
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SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14