SAMA5D42_14 Datasheet, PDF (674/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Table 32-55. Register Mapping (Continued)
Offset
Register
0x00000140
Overlay 1 Channel Enable Register
0x00000144
Overlay 1 Channel Disable Register
0x00000148
Overlay 1 Channel Status Register
0x0000014C
Overlay 1 Interrupt Enable Register
0x00000150
Overlay 1 Interrupt Disable Register
0x00000154
Overlay 1 Interrupt Mask Register
0x00000158
Overlay 1 Interrupt Status Register
0x0000015C
Overlay 1 DMA Head Register
0x00000160
Overlay 1 DMA Address Register
0x00000164
Overlay 1 DMA Control Register
0x00000168
Overlay 1 DMA Next Register
0x0000016C
Overlay 1 Configuration Register 0
0x00000170
Overlay 1 Configuration Register 1
0x00000174
Overlay 1 Configuration Register 2
0x00000178
Overlay 1 Configuration Register 3
0x0000017C
Overlay 1 Configuration Register 4
0x00000180
Overlay 1 Configuration Register 5
0x00000184
Overlay 1 Configuration Register 6
0x00000188
Overlay 1 Configuration Register 7
0x0000018C
Overlay 1 Configuration Register 8
0x00000190
Overlay 1 Configuration Register 9
0x00000194–0x0000023C Reserved
0x00000240
Overlay 2 Channel Enable Register
0x00000244
Overlay 2 Channel Disable Register
0x00000248
Overlay 2 Channel Status Register
0x0000024C
Overlay 2 Interrupt Enable Register
0x00000250
Overlay 2 Interrupt Disable Register
0x00000254
Overlay 2 Interrupt Mask Register
0x00000258
Overlay 2 Interrupt Status Register
0x0000025C
Overlay 2 DMA Head Register
0x00000260
Overlay 2 DMA Address Register
0x00000264
Overlay 2 DMA Control Register
0x00000268
Overlay 2 DMA Next Register
0x0000026C
Overlay 2 Configuration Register 0
0x00000270
Overlay 2 Configuration Register 1
0x00000274
Overlay 2 Configuration Register 2
0x00000278
Overlay 2 Configuration Register 3
674
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
Name
LCDC_OVR1CHER
LCDC_OVR1CHDR
LCDC_OVR1CHSR
LCDC_OVR1IER
LCDC_OVR1IDR
LCDC_OVR1IMR
LCDC_OVR1ISR
LCDC_OVR1HEAD
LCDC_OVR1ADDR
LCDC_OVR1CTRL
LCDC_OVR1NEXT
LCDC_OVR1CFG0
LCDC_OVR1CFG1
LCDC_OVR1CFG2
LCDC_OVR1CFG3
LCDC_OVR1CFG4
LCDC_OVR1CFG5
LCDC_OVR1CFG6
LCDC_OVR1CFG7
LCDC_OVR1CFG8
LCDC_OVR1CFG9
–
LCDC_OVR2CHER
LCDC_OVR2CHDR
LCDC_OVR2CHSR
LCDC_OVR2IER
LCDC_OVR2IDR
LCDC_OVR2IMR
LCDC_OVR2ISR
LCDC_OVR2HEAD
LCDC_OVR2ADDR
LCDC_OVR2CTRL
LCDC_OVR2NEXT
LCDC_OVR2CFG0
LCDC_OVR2CFG1
LCDC_OVR2CFG2
LCDC_OVR2CFG3
Access
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
–
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Reset
–
–
0x00000000
–
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
–
–
0x00000000
–
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000