405EZ Datasheet, PDF (8/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Power PC 405 Processor Core
The PPC405 core is a fixed-point, 32-bit RISC processor.
Features include:
• Five-stage pipeline with single-cycle execution of most instructions, including loads and stores
• Separate, configurable 16 KB D- and I-caches, both 2-way set associative
• Thirty-two 32-bit general purpose registers (GPRs)
• Unaligned load/store support
• Hardware multiply/divide
• Parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (TLB)
• Double word instruction fetch from cache
• Translation of the 4GB logical address space into physical addresses
• On-chip memory (OCM) interface
• Built-in timer and debug support
• Power management
• 32-bit DCR interface
Internal Buses
The PPC405EZ contains three internal buses: the on-chip peripheral bus (OPB), the processor local bus (PLB),
and the device control register (DCR) bus. High bandwidth devices such as the processor and the DMA core utilize
the PLB. Lower bandwidth I/O interfaces such as communications and timer interfaces utilize the OPB.
OPB
The OPB provides 32-bit address and data interfaces, and operates up to 83MHz. There is a bridge between the
OPB and the PLB.
Features include:
• - Pipelined read support
• - Dynamic bus sizing
• - Single-cycle data transfer between masters and slaves
PLB
The Processor Local Bus (PLB) is a high-performance on-chip bus used to connect PLB-equipped master and
slave devices to the PPC405 CPU. It provides a 64-bit data path with 32-bit addressing and operates at up
to166MHz. There is a bridge between the PLB and the OPB.
Features include:
• Overlapping read and write transfers
• Decoupled address and data buses
• Address pipelining
• Late master request abort capability
• Hidden (overlapped) bus request/grant protocol
• Bus arbitration-locking mechanism
• Byte-enable capability allows for unaligned half word transfers and 3-B transfers
• Support for 16-, 32-, and 64-B line data transfers
• Read word address capability
• Sequential burst protocol
• Guarded and unguarded memory transfers
• DMA buffered, flyby, peripheral-to-memory, memory-to-peripheral, and DMA memory-to-memory operations
8
AMCC Proprietary