405EZ Datasheet, PDF (5/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Block Diagram
Figure 1. PPC405EZ Embedded Controller Functional Block Diagram
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
32 KB
SRAM
Timers
MMU
D-OCM
I-OCM
PowerPC
405 Core
JTAG
Trace
16KB D-Cache 16KB I-Cache
DCRs
DCR
Bus
OCM
Ctrl
Arbiter
UART CAN
x2 x2
IIC/
BSC
SPI
(SCP)
GPIO
Timer/
PWM
DAC
On-chip Peripheral Bus (OPB)
ADC
DMA
Controller
(4-Channel)
OPB/PLB
Bridges
MAL
Ethernet ^{USB 1.1}
10/100 ^Host/Dev
IEEE
1588
PTP
Arbiter
Processor Local Bus (PLB) 64 bit, PLB3
External
Bus
Controller
NAND
Flash
Controller
PHY
MII
The PPC405EZ is designed using the IBM Microelectronics Blue Logic^TM methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect^TM Bus Architecture.
AMCC Proprietary
5