405EZ Datasheet, PDF (52/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision Log
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Date
01/13/2006
03/09/2006
04/10/2006
04/21/2006
05/12/2006
06/13/2006
07/18/2006
08/8/2006
08/30/2006
09/05/2006
09/18/2006
10/18/2006
02/07/2007
Version
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
Contents of Modification
Initial distribution for review.
Misc. corrections.
Correct AMCC address.
Add revision log.
Change three EBC signals to match previous chips (HoldAck, HoldPri, and HoldReq).
Misc. corrections.
Add pull-up/pull-down notes.
Update clock timings.
Correct Bootstrap pin numbers.
Correct pin number swaps.
Add circuit types to signal descriptions.
Reduce recommended logic voltage range by 0.025V.
Add 266MHz and 333MHz CPU speeds.
Allow 3.3V power supply for ADC and DAC.
Add output currents to I/O tables.
Correct Recommended Operating Conditions.
Remove 5V Tolerant input current curve.
Add output current values (based on I/O circuit type) to I/O tables
Correct filter circuit component units-of-measure from m to μ.
Correct ADC_In6 and ADC_In7 pins assignment.
Correct EBC_Dbus24 and EBC_Dbus25 pins assignment.
Change signal name NI_DivClk to PWM_DivClk.
Add typical DC power requirements.
Split OV_DD voltage pins into two sets so EBC voltage can be different from other I/O if necessary.
Update from engineering review.
Timing updates.
Chameleon Timer and IEEE 1588 PTP updates.
Add package thermal data.
Analog voltage filter updates.
Part number updates.
Remove TE package and references to “industrial” from thermal package data.
Remove watermark and change status to Preliminary.
Add heat sink data and increase case temperature range to +105°C.
Change minimum CPU frequency to 133.33MHz.
Add DC power supply current load values.
Change pin assignments for the Ethernet Tx and Rx data signals.
Alter prefixes and remove extraneous characters from some signal names to make them
consistent with the UM and previous chips. There are no functional or pin (ball) number changes.
Correct JTAG ID.
Remove CAN disable option.
Reduce maximum SPI speed.
Change power specifications in Description.
Add link to AMCC partners supplying probes.
Deleted internal clock signal timing table.
Added PerClk signal to external peripheral timing table.
Restrict ADC and DAC analog voltage filters to OV_DD1.
Typographical Updates
52
AMCC Proprietary