405EZ Datasheet, PDF (50/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 16. I/O Specifications—416 MHz CPU
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
2. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) (T_IH min)
External Peripheral Interface
PerClk
na
na
CRAM_Clk
na
na
CRAM_AdV
na
na
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
7.2
2
PerAddr04:31
na
na
7.35
2.16
BusReq
na
na
7.3
2.1
PerCS0:7
na
na
7.3
2.1
PerData00:31
1.6
2.1
7.5
2.1
HoldReq
1.6
2.1
na
na
HoldAck
na
na
7.3
2.1
HoldPri
1.6
2.1
na
na
PerOE
na
na
7.35
2.15
PerReady
1.6
2.1
na
na
PerRW
na
na
7.35
2.15
PerWBE0:3
na
na
7.3
2.15
NFALE
7.1
0.9
NFCE0
7.1
0.9
NFCLE
7.1
0.9
NFData0:7
9.2
-0.7
7.1
0.9
NFRB
10
0
NFRE
7.1
0.9
NFWE
DMAAck
DMAEOT/TC
DMAReq
7.1
0.9
na
na
7.3
2.1
5
0.9
na
na
Output Current (mA)
I/O H
I/O L
(minimum) (minimum)
Clock
19.1
8.7
na
19.1
8.7
na
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
na
na
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
na
na
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
na
na
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
PerClk/
CRAM_Clk
19.1
8.7
19.1
8.7
19.1
8.7
Notes
50
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