405EZ Datasheet, PDF (14/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the
various sources of interrupts and the PPC405 processor.
Features include:
• 32 interrupt sources supported (5 external)
• Generate interrupt on level (high or low) or edge (rising or falling)
• Programmable as synchronous (edge-capture or level-sensitive) or asynchronous (edge- or level-sensitive
triggering)
• Each interrupt source/bit programmable as critical or non critical
• 32-bit DCR bus interface
• Optional interrupt handler vector generation
– Programmable vector base address
– Programmable vector offset size
– Programmable interrupt priority ordering
• Programmable polarity for all interrupt types
• Interrupts of the same type do not need to be in contiguous bit positions
• Status registers provide: current state of all interrupts, current state of enabled interrupts
10/100 Ethernet
The Ethernet support provides a single 10/100 Mbps interface.
Features include:
• ANSI/IEEE Std. 802.3 and IEEE 802.3u supplement compliant
• Half-duplex and full-duplex supported
• MII interface to external PHY
• 512 byte receive FIFOs with programmable thresholds
• FCS control for transmit/receive packets
• Multiple packet handling in transmit and receive FIFOs
• Unicast, multicast, broadcast, and promiscuous address filtering
• Two 64-bit hash filters for unicast and multicast frames
• Automatic retransmission of collided frames
• Runt frame rejection
• Programmable inter-frame gap
• IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame
transmitting)
• Wake-on-LAN and Power-over-Internet supported
• Programmable internal/external loopback capabilities
• 32-bit OPB slave (MAC) and PLB master (MAL) interfaces
• Extensive error/status vector generation for each processed packet
• VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard)
• Programmable automatic source address inclusion/replacement for transmit packets
• Programmable automatic Pad/FCS stripping for receive packets
• Programmable VLAN Tag inclusion/replacement for transmit packets
IEEE 1588 Precision Timing Protocol Controller
In a distributed control system containing multiple clocks, this feature defines messages used to exchange timing
information for precision network synchronization purposes. A second UIC in the PPC405EZ is dedicated to
generating snapshot triggers to the IEEE 1588 PTP controller from any interrupt source in the chip.
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