405EZ Datasheet, PDF (41/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Ratings and Specifications
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Symbol
Value
Unit
Notes
Supply Voltage (Internal Logic)
Non-EBC I/O Supply Voltage
EBC I/O Supply Voltage
PLL Analog Supply Voltage
ADC Analog Supply Voltage
DAC Analog Supply Voltage
Input Voltage (3.3V LVTTL receivers)
Input Voltage (5.0V LVTTL receivers)
Storage Temperature Range
Case temperature under bias
Junction temperature
V_DD
OV_DD1
OV_DD2
PLL_AV_DD
ADC_AV_DD
DAC_AV_DD
V_IN
V_IN
T_STG
T_C
T_JMax
0 to +1.6
0 to +3.6
0 to +3.6
0 to +1.6
0 to +3.465
0 to +3.465
0 to +3.6
0 to +5.5
-55 to +150
-40 to +120
+125
V
V
V
3
V
V
V
V
V
°C
°C
°C
1. All voltages are specified with respect to GND.
2. The analog voltages use for the system PLL, the ADC, and the DAC can be derived from V_DD and OV_DD1, but must be filtered
as shown below before entering the PPC405EZ. Use a separate filter for each voltage. The maximum value for ADC_PLL and
DAC_PLL must be limited to the values shown in this table.
3. OV_DD2 must be limited to a maximum value of +3.3V if CRAM/PSRAM devices are attached to the EBC interface. This is a
limitation imposed by the CRAM/PSRAM devices, not the PPC405EZ.
V_DD
OV_DD1
L1
C1
GND
L1
C1
C2
GND
PLL_AV_DD
PLL_AGND
ADC_PLL, DAC_PLL
ADC_GND, DAC_GND
L1 – Murata BLM18AG121SN1D
C1 – 0.1 μF ceramic
L1 – Murata BLM18AG121SN1D
C1 – 0.1 μF ceramic
C2 – 0.01μF ceramic
AMCC Proprietary
41