405EZ Datasheet, PDF (12/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
• Loopback controls for isolating communications link faults
• Break, parity, overrun, framing error simulation
• OPB interface with optional DMA support
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
IIC Bus Interface
The Inter-Integrated Circuit (IIC) interface provides a Philips I²C^® compatible interface operating up to 400kHz
either as a master, a slave, or both with a bootstrap controller (BSC) included. During chip reset, the bootstrap
controller can read configuration data from an IIC compatible memory device (e.g., EEPROM). This data can be
used to replace the default configuration settings provided by the chip.
Features include:
• One IIC channel
• Compliant with Philips Semiconductors I²C Specification, dated 1995
• 100 kHz or 400 kHz operation
• 8-bit data
• 10- or 7-bit address
• Slave Transmit and Receive
• Master Transmit and Receive
• Multiple bus masters supported
• Programmable as master, slave, or master/slave
• Boot parameters read from IIC attached memory with IIC bootstrap controller
• 32-bit OPB slave interface
Serial Peripheral Interface (SPI/SCP)
The Serial Peripheral Interface (SPI) (also known as the Serial Communications Port or SCP) is a full-duplex,
synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SPI is a
master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features include:
• One SPI/SCP channel, full duplex synchronous
• SPI/SCP master
• Up to 40 MHz
• Programmable internal loopback capabilities
• Multi-master protocol supported
• Independent masking of all interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive
FIFO full, receive FIFO underflow, receive FIFO overflow)
• Dynamic control of serial bit rate of data transfer (serial-master mode only)
• Data Item size for each data transfer under programmer control (4-to-16 bits)
• Boot from SPI supported
• 32-bit OPB slave interface
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