405EZ Datasheet, PDF (38/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
External Peripheral Interface
CRAM_AdV
Address valid signal for PSRAM/CRAM support.
O
3.3V LVTTL
CRAM_Clk
PerAddr04:31
PerClk gated for PSRAM/CRAM support.
Memory address bus 4:31.
O
3.3V LVTTL
O
3.3V LVTTL
BusReq
External PLB bus request.
O
3.3V LVTTL
PerClk
PerCS0:7
Clock output.
Chip selects 0:7.
O
3.3V LVTTL
O
3.3V LVTTL
PerData00:31
PerOE
Memory data bus 0:31.
Output enable.
I/O 3.3V LVTTL
O
3.3V LVTTL
PerReady
Wait for PSRAM/CRAM support.
I
3.3V LVTTL
PerRW
PerWBE0:3
Read/Write.
Write bus enable 0:3.
O
3.3V LVTTL
O
3.3V LVTTL
DMAAck
DMAEOT/TC
External DMA peripheral acknowledge.
External DMA peripheral end-of-transmission/terminal count.
O
3.3V LVTTL
I/O 3.3V LVTTL
DMAReq
HoldReq
HoldAck
External peripheral DMA request.
External request for bus access.
External request acknowledge.
I
3.3V LVTTL
I
3.3V LVTTL
O
3.3V LVTTL
HoldPri
External bus request priority.
NAND Flash Interface
I
3.3V LVTTL
NFALE
Address latch enable.
O
3.3V LVTTL
NFCE0:3
Cchip selects 0:3.
O
3.3V LVTTL
NFCLE
NFData0:7
Command latch enable.
Data bits 0:7
O
3.3V LVTTL
I/O 3.3V LVTTL
NFRB
Read/Busy. If low, indicates that Read/Erase command is in process.
If high, indicates that the command is complete.
I
3.3V LVTTL
NFRE
Read enable.
O
3.3V LVTTL
NFWE
Write enable.
Serial Peripheral Interface
O
3.3V LVTTL
SPI_ClkOut
Serial peripheral interface clock.
O
3.3V LVTTL
SPI_DI
SPI_DO
Master and slave input.
Master and slave output.
I
3.3V LVTTL
O
3.3V LVTTL
SPI_SS0:3
Slave Select 0:3.
O
3.3V LVTTL
SPI_SS_In
Slave Select Input for multi-master collision detection.
I
3.3V LVTTL
Notes
5
5
5
5
38
AMCC Proprietary