405EZ Datasheet, PDF (6/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Address Maps
The PPC405EZ incorporates two address maps. The first address map defines the possible use of addressable
memory regions that the processor can access. The second address map defines Device Configuration Register
(DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EZ processor through
the use of mtdcr and mfdcr instructions.
Table 1. System Memory Address Map (4GB System Memory)
Function
Subfunction
Start Address
End Address
General Use
0x 0000 0000
0x DFFF FFFF
Reserved
0x E000 0000
0x EF60 02FF
UART 0 Registers
0x EF60 0300
0x EF60 03FF
UART 1 Registers
0x EF60 0400
0x EF60 04FF
IIC Registers
0x EF60 0500
0x EF60 05FF
OPB Arbiter Registers
0x EF60 0600
0x EF60 06FF
GPIO 0 Controller Registers
0x EF60 0700
0x EF60 07FF
GPIO 1 Controller Registers
0x EF60 0800
0x EF60 08FF
EMAC Registers
0x EF60 0900
0x EF60 09FF
Reserved
0x EF60 0A00
0x EF60 0FFF
CAN 0 Registers
0x EF60 1000
0x EF60 17FF
CAN 1 Registers
0x EF60 1800
0x EF60 1FFF
Chameleon Timer Registers
0x EF60 2000
0x EF60 27FF
IEEE 1588 Sync Controller Registers
0x EF60 2800
0x EF60 2FFF
USB 1.1 Host Registers
0x EF60 3000
0x EF60 31FF
Reserved
0x EF60 3200
0x EF60 32FF
DAC Registers
0x EF60 3300
0x EF60 33FF
ADC Registers
0x EF60 3400
0x EF60 34FF
Serial Communication Port Registers
0x EF60 3500
0x EF60 35FF
Reserved
0x EF60 3600
0x EF63 FFFF
USB 1.1 Device Registers
0x EF64 0000
0x EF67 FFFF
Reserved
0x EF68 0000
0x FFDF FFFF
Boot Address Range
0x FFE0 0000
0x FFFF FFFF
Notes:
1. If peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.
2. After the boot process, software may reassign the boot memory regions for other uses.
Size
3.7GB
256B
256B
256B
256B
256B
256B
256B
2KB
2KB
2KB
2KB
512B
256B
256B
256B
262KB
2 MB
6
AMCC Proprietary