405EZ Datasheet, PDF (43/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 9. Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
Logic Supply Voltage
V_DD
+1.425
+1.5
+1.575
V
I/O Supply Voltage (for non-EBC I/O)
OV_DD1
+3.0
+3.3
+3.6
V
I/O Supply Voltage (for EBC I/O)
OV_DD2
+3.0
+3.3
+3.6
V
1
(see Note 1)
PLL Analog Supply Voltage
PLL_AV_DD
+1.4
+1.5
+1.6
V
ADC Analog Supply Voltage
ADC_AV_DD
+3.135
+3.3
+3.465
V
DAC Analog Supply Voltage
DAC_AV_DD
+3.135
+3.3
+3.465
V
I/O Input Low (3.3V LVTTL)
V_IL
0
+0.8
V
I/O Input High (3.3V LVTTL)
V_IH
+2.0
+3.6
V
I/O Output Low (3.3V LVTTL)
V_OL
0
+0.4
V
I/O Output High (3.3V LVTTL)
V_OH
+2.4
+3.6
V
I/O High (USB, 5V tolerant)
V_OH
+2.8
V
I/O Low (USB, 5V tolerant)
V_OL
+0.3
V
I/O Input High (IIC)
V_IH
0.7OV_DD
OV_DD + 0.3
V
I/O Input Low (IIC)
V_IL
−0.3
+0.3OV_DD
V
I/O Output High (IIC)
V_IH
V
I/O Output Low (IIC)
V_OL
0
+0.4
V
Input Leakage Current
(no pull-up or pull-down)
I_IL1
0
0
μA
Input Leakage Current
(with internal pull-down)
I_IL2
0
200
μA
I/O Maximum Allowable Overshoot
(3.3V LVTTL)
V_MAO
+3.9
V
I/O Maximum Allowable Undershoot
(3.3V LVTTL)
V_MAU
−0.6
V
Case Temperature
T_C
−40
+105
°C
Notes:
1. When using CRAM or PSRAM memory on the EBC interface, this voltage must be limited to a maximum of +3.3V. This is a limitation
imposed by the CRAM/PSRAM devices, not the PPC405EZ.
Table 10. Input Capacitance
Parameter
3.3V LVTTL I/O
USB 5V Tolerant I/O
IIC I/O
Symbol
C_IN1
C_IN2
C_IN3
Maximum
1.9
3.2
5.8
Unit
pF
pF
pF
Notes
AMCC Proprietary
43