405EZ Datasheet, PDF (39/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
UART Peripheral Interface
UART0_CTS
Clear to send.
I
3.3V LVTTL
UART0_DCD
UART0_DSR
Data carrier detect.
Data set ready.
I
3.3V LVTTL
I
3.3V LVTTL
UART0_DTR
Data terminal ready.
O
3.3V LVTTL
UART0_RI
UART0_RTS
Ring indicator.
Request to send.
I
3.3V LVTTL
O
3.3V LVTTL
UART0_Rx
UART0_Tx
Receive data.
Transmit data.
I
3.3V LVTTL
O
3.3V LVTTL
UART1_Rx
Receive data
I
3.3V LVTTL
UART1_Tx
USB Interface
Transmit data
O
3.3V LVTTL
USB1FClk
48 MHz clock for USB
I
3.3V LVTTL
USB1DEV0
USB1DEV0
USB1HOST0
USB1HOST0
Device differential + data signal
Device differential − data signal
Host 0 differential + data signal
Host 0 differential − data signal
I/O
5V tolerant
USB Diff
I/O
5V tolerant
USB Diff
I/O
5V tolerant
USB Diff
I/O
5V tolerant
USB Diff
USB1HOST1
Host 1 differential + data signal
I/O
5V tolerant
USB Diff
USB1HOST1
Host 1 differential − data signal
I/O
5V tolerant
USB Diff
Notes
5
5
AMCC Proprietary
39