405EZ Datasheet, PDF (49/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 15. I/O Specifications—All CPU Speeds (Sheet 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected.
2. For all interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
3. Maximum skew between IIC output signals is 6ns.
4. Maximum skew between all SPI output signals is 3ns. All SPI inputs signals are latched with less than 4ns of skew between
channels.
5. Maximum skew between all PWM output signals is 3.75ns. All PWM input signals are latched with less than 2.5ns of skew
between channels.
Signal
ADC_InTrig
ADC_VRef
DAC_CRef
DAC_IOutP
DAC_IPTrig
DAC_IRRef
DAC_VRef
DAC_GRef
PWM_DivClk
PWM_OE[0]
PWM_OE[1:3]
PWM_TBA
PWM_1:15
IEEE_1588TS
Interrupts Interface
[IRQ0:4]
JTAG Interface
TCK
TDI
TDO
TMS
TRST
System Interface
GPIO000:31
GPIO100:20
Halt
SysErr
SysReset
TestEn
DebugEn
SysClk
Input (ns)
Setup Time Hold Time
(T_IS min) (T_IH min)
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
22.5
0
na
na
na
na
25
0
22.5
0
na
na
na
na
na
na
na
na
na
na
na
na
na
na
22.5
0
na
na
na
na
15
25.5
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
Output Current (mA)
I/O H
(min)
I/O L
(min)
na
na
na
na
na
na
na
na
19.1
8.7
na
na
na
na
na
na
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
na
na
na
na
19.1
8.7
na
na
na
na
19.1
8.7
19.1
8.7
na
na
19.1
8.7
19.1
8.7
na
na
na
na
na
na
Clock
Notes
5
5
5
5
5
TCK
TCK
TCK
TCK
TCK
TCK
async
async
AMCC Proprietary
49