405EZ Datasheet, PDF (11/54 Pages) Applied Micro Circuits Corporation – PowerPC 405EZ Embedded Processor

PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Universal Serial Bus Specification
Controller Area Network (CAN)
The CAN controller module supports the concept of mailboxes. It contains 32 receive buffers, each one with its
own message filter, and 32 transmit buffers with a prioritized arbitration scheme. For optimal support of Higher
Level Protocols (HLP) such as DeviceNet or SDC, the message filter covers the first two data bytes.
Features include:
• CAN 2.0B protocol compliant
• ISO 11898-1 compliant
• 32 Transmit message holding registers, programmable priority arbitration
• Message abort command supported
• 32 Receive buffers (each with own message filter)
– Message filtering: ID, IDE, Remote Transmission Request (RTR), data byte 1, and data byte 2
• Message buffers can be linked together to build bigger message arrays
• Automatic RTR response handler
• Message Abort command supported
• Maximum baud rate of 1Mbps with 8MHz system clock
• Listen-only for debugging supported
• Global masking supported
• 32-bit OPB slave interface
• Internal loopback
UART
The Universal Asynchronous Receiver/Transmitter (UART) interface provides two ports. The UART performs
serial-to-parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial
conversion on data received from the processor.
Features include:
• Two ports (UART_0 and UART_1)
• Software modem control functions (CTS, RTS, DSR, DTR, RI, DCD) on UART_0
• Programmable auto flow (data flow controlled by RTS and CTS signals)
• 5-, 6-, 7-, or 8-bit characters
• Programmable start, stop, parity bit insertion
• 64 byte FIFOs to buffer Tx and Rx data
• LIN sub-bus specification compliant - line break generation/detection and false start bit detection
• Programmable internal/external loopback capabilities
• Low Power and Sleep mode
• Register conformance (after reset) to configuration of the NS16450 register set
• Hold and shift registers (eliminate need for precise synchronization between processor and serial data in
character mode)
• Complete status reporting
• Full prioritized interrupt system controls
• Independently controlled transmit, receive, line status, and data set interrupts
• Programmable baud generator (divides serial clock input and generates 16x clock)
• Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial
data
• Even, odd, or no-parity bit generation and detection
• 1-, 1.5-, or 2-stop bit generation
• Variable baud rate
• Internal diagnostic capability
AMCC Proprietary
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