EP2S90F1020C4N Datasheet, PDF (84/238 Pages) Altera Corporation – The Stratix II family offers the following features

I/O Structure
Figure 2–51 shows the IOE in bidirectional configuration.
Figure 2–51. Stratix II IOE in Bidirectional I/O Configuration Note (1)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
clkout
ce_out
aclr/apreset
Chip-Wide Reset
sclr/spreset
clkin
ce_in
OE Register
D
Q
ENA
CLRN/PRN
OE Register
t_CO Delay
V_{CCIO PCI Clamp (2)}
V_CCIO
Programmable
Pull-Up
Resistor
Output Register
D
Q
Output
Pin Delay
ENA
Drive Strength Control
CLRN/PRN Open-Drain Output
Input Pin to
Logic Array Delay
Input Register
D
Q
Input Pin to
Input Register Delay
On-Chip
Termination
Bus-Hold
Circuit
ENA
CLRN/PRN
Notes to Figure 2–51:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The optional PCI clamp is only available on column I/O pins.
2–76
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007