EP2S90F1020C4N Datasheet, PDF (43/238 Pages) Altera Corporation – The Stratix II family offers the following features

Stratix II Architecture
Similar to all RAM blocks, M-RAM blocks can have different clocks on
their inputs and outputs. Either of the two clocks feeding the block can
clock M-RAM block registers (renwe, address, byte enable, datain, and
output registers). The output register can be bypassed. The six labclk
signals or local interconnect can drive the control signals for the A and B
ports of the M-RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals as shown in Figure 2–23.
Figure 2–23. M-RAM Block Control Signals
Dedicated
Row LAB
6
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_a
renwe_a
aclr_b
clock_b
clock_a
aclr_a
renwe_b
clocken_b
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
The R4, R24, C4, and direct link interconnects from adjacent LABs on
either the right or left side drive the M-RAM block local interconnect. Up
to 16 direct link input connections to the M-RAM block are possible from
the left adjacent LABs and another 16 possible from the right adjacent
LAB. M-RAM block outputs can also connect to left and right LABs
through direct link interconnect. Figure 2–24 shows an example floorplan
for the EP2S130 device and the location of the M-RAM interfaces.
Figures 2–25 and 2–26 show the interface between the M-RAM block and
the logic array.
Altera Corporation
May 2007
2–35
Stratix II Device Handbook, Volume 1