EP2S90F1020C4N Datasheet, PDF (215/238 Pages) Altera Corporation – The Stratix II family offers the following features

DC & Switching Characteristics
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions (Figure 5–9). Therefore, any distortion on the input
clock and the input clock buffer affect the output DCD.
Figure 5–9. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
IOE
clk
INPUT
VCC
V_{CC DFF}
PRN
DQ
CLRN
inst2
OUTPUT
output
GND
NOT
inst8
DFF
PRN
DQ
CLRN
inst3
Altera Corporation
April 2011
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Tables 5–80 through 5–87 give the maximum DCD in absolution
derivation for different I/O standards on Stratix II devices. Examples are
also provided that show how to calculate DCD as a percentage.
Table 5–80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 1
of 2) Note (1)
Row I/O Output
Standard
3.3-V LVTTTL
3.3-V LVCMOS
2.5 V
Maximum DCD for Non-DDIO Output
-3 Devices
-4 & -5 Devices
Unit
245
275
ps
125
155
ps
105
135
ps
5–79
Stratix II Device Handbook, Volume 1