EP2S90F1020C4N Datasheet, PDF (204/238 Pages) Altera Corporation – The Stratix II family offers the following features

Timing Model
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 2 of 2)
Input I/O Standard
1.8-V HSTL Class II
PCI (1)
PCI-X (1)
1.2-V HSTL (2)
Differential SSTL-2 Class I
(1), (3)
Differential SSTL-2 Class II
(1), (3)
Differential SSTL-18 Class I
(1), (3)
Differential SSTL-18 Class II
(1), (3)
1.8-V Differential HSTL
Class I (1), (3)
1.8-V Differential HSTL
Class II (1), (3)
1.5-V Differential HSTL
Class I (1), (3)
1.5-V Differential HSTL
Class II (1), (3)
HyperTransport technology
(4)
LVPECL (1)
LVDS (5)
LVDS (6)
Column I/O Pins (MHz)
-3 -4
-5
500 500 500
500 500 450
500 500 450
280
-
-
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
-
-
-
-
-
-
-
-
-
-
-
-
Row I/O Pins (MHz)
-3 -4
-5
500 500 500
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
520 520 420
-
-
-
520 520 420
-
-
-
Dedicated Clock Inputs
(MHz)
-3
-4 -5
500 500 500
500 500 400
500 500 400
280
-
-
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
717 717 640
450 450 400
717 717 640
450 450 400
Notes to Table 5–77:
(1) Row clock inputs don’t support PCI, PCI-X, LVPECL, and differential HSTL and SSTL standards.
(2) 1.2-V HSTL is only supported on column I/O pins.
(3) Differential HSTL and SSTL standards are only supported on column clock and DQS inputs.
(4) HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
(5) These numbers apply to I/O pins and dedicated clock pins in the left and right I/O banks.
(6) These numbers apply to dedicated clock pins in the top and bottom I/O banks.
5–68
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011