EP2S90F1020C4N Datasheet, PDF (234/238 Pages) Altera Corporation – The Stratix II family offers the following features

Document Revision History
Table 5–103. Document Revision History (Part 2 of 3)
Date and
Document
Version
Changes Made
Summary of Changes
August, 2006, Updated Table 5–73, Table 5–75, Table 5–77,
—
v4.2
Table 5–78, Table 5–79, Table 5–81, Table 5–85, and
Table 5–87.
April 2006, v4.1
● Updated Table 5–3.
● Updated Table 5–11.
● Updated Figures 5–8 and 5–9.
● Added parallel on-chip termination information to
“On-Chip Termination Specifications” section.
● Updated Tables 5–28, 5–30,5–31, and 5–34.
● Updated Table 5–78, Tables 5–81 through 5–90,
and Tables 5–92, 5–93, and 5–98.
● Updated “PLL Timing Specifications” section.
● Updated “External Memory Interface
Specifications” section.
● Added Tables 5–95 and 5–101.
● Updated “JTAG Timing Specifications” section,
including Figure 5–10 and Table 5–102.
● Changed 0.2 MHz to 2 MHz in
Table 5–93.
● Added new spec for half period
jitter (Table 5–101).
● Added support for PLL clock
switchover for industrial
temperature range.
● Changed f_{I N P F D} (min) spec from
4 MHz to 2 MHz in Table 5–92.
● Fixed typo in t_{O U T J I T T E R}
specification in Table 5–92.
● Updated V_{D I F} AC & DC max
specifications in Table 5–28.
● Updated minimum values for t_{J C H} ,
t_{J C L} , and t_{J P S U} in Table 5–102.
● Update maximum values for t_{J P C O},
t_{J P Z X} , and t_{J P X Z} in Table 5–102.
December 2005, ● Updated “External Memory Interface
—
v4.0
Specifications” section.
● Updated timing numbers throughout chapter.
July 2005, v3.1 ● Updated HyperTransport technology information in
—
Table 5–13.
● Updated “Timing Model” section.
● Updated “PLL Timing Specifications” section.
● Updated “External Memory Interface
Specifications” section.
May 2005, v3.0 ● Updated tables throughout chapter.
—
● Updated “Power Consumption” section.
● Added various tables.
● Replaced “Maximum Input & Output Clock Rate”
section with “Maximum Input & Output Clock Toggle
Rate” section.
● Added “Duty Cycle Distortion” section.
● Added “External Memory Interface Specifications”
section.
March 2005,
Updated tables in “Internal Timing Parameters”
—
v2.2
section.
January 2005, Updated input rise and fall time.
—
v2.1
5–98
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011