EP2S90F1020C4N Datasheet, PDF (76/238 Pages) Altera Corporation – The Stratix II family offers the following features

PLLs & Clock Networks
Enhanced PLLs
Stratix II devices contain up to four enhanced PLLs with advanced clock
management features. Figure 2–44 shows a diagram of the enhanced PLL.
Figure 2–44. Stratix II Enhanced PLL Note (1)
VCO Phase Selection
Selectable at Each
PLL Output Port
INCLK[3..0]
4
Global or
Regional
Clock (4)
Clock
Switchover
Circuitry
Phase Frequency
Detector
Spread
Spectrum
/n
Charge
Loop
8
PFD
Pump
Filter
VCO
(2)
FBIN
/m
Lock Detect
& Filter
From Adjacent PLL
Post-Scale
Counters
/c0
/c1
/c2
6
/c3
/c4
/c5
4
Global
Clocks
8
Regional
Clocks
6
I/O Buffers (3)
to I/O or general
routing
Shaded Portions of the
PLL are Reconfigurable
VCO Phase Selection
Affecting All Outputs
Notes to Figure 2–44:
(1) Each clock source can come from any of the four clock pins that are physically located on the same side of the device
as the PLL.
(2) If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
(3) Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
(4) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
2–68
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007