EP2S90F1020C4N Datasheet, PDF (175/238 Pages) Altera Corporation – The Stratix II family offers the following features

DC & Switching Characteristics
Table 5–41. M4K Block Internal Timing Microparameters (Part 2 of 2) Note (1)
Symbol
Parameter
-3 Speed
Grade (2)
Min
(4)
Max
-3 Speed
Grade (3)
Min
(4)
Max
-4 Speed
Grade
Min
(5)
Max
-5 Speed
Grade
Unit
Min
(4)
Max
t_{M 4 K DATA A S U} A port data setup time
22
23
25
29
ps
before clock
25
t_{M 4 K D ATA A H}
A port data hold time
203
213
233
272
ps
after clock
233
t_{M 4 K A D D R A S U} A port address setup
22
23
25
29
ps
time before clock
25
t_{M 4 K A D D R A H} A port address hold time 203
213
233
272
ps
after clock
233
t_{M 4 K DATA B S U} B port data setup time
22
23
25
29
ps
before clock
25
t_{M 4 K D ATA B H}
B port data hold time
203
213
233
272
ps
after clock
233
t_{M 4 K R A D D R B S U} B port address setup
22
23
25
29
ps
time before clock
25
t_{M 4 K R A D D R B H} B port address hold time 203
213
233
272
ps
after clock
233
t_{M 4 K D ATA C O 1}
Clock-to-output delay
when using output
registers
334 524 334 549 319 601 334 701 ps
334
t_{M 4 K D ATA C O 2}
(6)
Clock-to-output delay 1,616 2,453 1,616 2,574 1,540 2,820 1,616 3,286 ps
without output registers
1,616
t_{M 4 K C L K H}
Minimum clock high time 1,250
1,312
1,437
1,675
ps
1,437
t_{M 4 K C L K L}
Minimum clock low time 1,250
1,312
1,437
1,675
ps
1,437
t_{M 4 K C L R}
Minimum clear pulse
144
151
165
192
ps
width
165
Notes to Table 5–41:
(1) F_MAX of M4K Block obtained using the Quartus II software does not necessarily equal to 1/TM4KRC.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(5) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
(6) Numbers apply to unpacked memory modes, true dual-port memory modes, and simple dual-port memory modes
that use locally routed or non-identical sources for the A and B port registers.
Altera Corporation
April 2011
5–39
Stratix II Device Handbook, Volume 1