EP2S90F1020C4N Datasheet, PDF (186/238 Pages) Altera Corporation – The Stratix II family offers the following features

Timing Model
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, intra-clock network skew
adder is not specified. Table 5–68 specifies the clock skew between any
two clock networks driving registers in the IOE.
Table 5–68. Clock Network Specifications
Name
Clock skew adder
EP2S15, EP2S30,
EP2S60 (1)
Clock skew adder
EP2S90 (1)
Clock skew adder
EP2S130 (1)
Clock skew adder
EP2S180 (1)
Description
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Min
Typ
Max Unit
±50
ps
±100
ps
±55
ps
±110
ps
±63
ps
±125
ps
±75
ps
±150
ps
Note to Table 5–68:
(1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
5–50
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011