EP2S90F1020C4N Datasheet, PDF (56/238 Pages) Altera Corporation – The Stratix II family offers the following features

PLLs & Clock Networks
PLLs & Clock
Networks
Stratix II devices provide a hierarchical clock structure and multiple PLLs
with advanced features. The large number of clocking resources in
combination with the clock synthesis precision provided by enhanced
and fast PLLs provides a complete clock management solution.
Global & Hierarchical Clocking
Stratix II devices provide 16 dedicated global clock networks and
32 regional clock networks (eight per device quadrant). These clocks are
organized into a hierarchical clock structure that allows for up to
24 clocks per device region with low skew and delay. This hierarchical
clocking scheme provides up to 48 unique clock domains in Stratix II
devices.
There are 16 dedicated clock pins (CLK[15..0]) to drive either the global
or regional clock networks. Four clock pins drive each side of the device,
as shown in Figures 2–31 and 2–32. Internal logic and enhanced and fast
PLL outputs can also drive the global and regional clock networks. Each
global and regional clock has a clock control block, which controls the
selection of the clock source and dynamically enables/disables the clock
to reduce power consumption. Table 2–8 shows global and regional clock
features.
Table 2–8. Global & Regional Clock Features
Feature
Number per device
Number available per
quadrant
Sources
Dynamic clock source
selection
Dynamic enable/disable
Global Clocks
16
16
Regional Clocks
32
8
CLK pins, PLL outputs, CLK pins, PLL outputs,
or internal logic
or internal logic
v (1)
v
v
Note to Table 2–8:
(1) Dynamic source clock selection is supported for selecting between CLKp pins and
PLL outputs only.
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. The global clock networks can be used as clock sources for all
resources in the device-IOEs, ALMs, DSP blocks, and all memory blocks.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin. The
2–48
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007