EP2S90F1020C4N Datasheet, PDF (159/238 Pages) Altera Corporation – The Stratix II family offers the following features

DC & Switching Characteristics
4. Record the time to V_MEAS.
5. Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 5–34 using the above equation. Figure 5–4 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
Figure 5–4. Output Delay Timing Reporting Setup Modeled by Quartus II
V_TT
V_CCIO
R_T
Output ^Output
R_S
Buffer
V_MEAS
C_L
Output_p
R_D
Output_n
GND
GND
Notes to Figure 5–4:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2) V_CCPD is 3.085 V unless otherwise specified.
(3) V_CCINT is 1.12 V unless otherwise specified.
Figures 5–5 and 5–6 show the measurement setup for output disable and
output enable timing.
Altera Corporation
April 2011
5–23
Stratix II Device Handbook, Volume 1