EP2S90F1020C4N Datasheet, PDF (223/238 Pages) Altera Corporation – The Stratix II family offers the following features

DC & Switching Characteristics
High-Speed I/O
Specifications
Table 5–88 provides high-speed timing specifications definitions.
Table 5–88. High-Speed Timing Specifications & Definitions
High-Speed Timing Specifications
Definitions
t_C
f_{H S C L K}
J
W
t_{R I S E}
t_{F A L L}
Timing unit interval (TUI)
f_{H S D R}
f_{H S D R D P A}
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter
Output jitter
t_DUTY
t_{L O C K}
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t_C /w).
Maximum/minimum LVDS data transfer rate (f_{H SD R} = 1/TUI), non-DPA.
Maximum/minimum LVDS data transfer rate (f_{H S D R D PA} = 1/TUI), DPA.
The timing difference between the fastest and slowest output edges,
including t_{C O} variation and clock skew. The clock is included in the TCCS
measurement.
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Table 5–89 shows the high-speed I/O timing specifications for -3 speed
grade Stratix II devices.
Table 5–89. High-Speed I/O Specifications for -3 Speed Grade (Part 1 of 2) Notes (1), (2)
Symbol
Conditions
f_{H S C L K} (clock frequency)
f_{H S C L K} = f_{H S D R} / W
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
-3 Speed Grade
Min Typ Max
16
520
16
500
150
717
Unit
MHz
MHz
MHz
Altera Corporation
April 2011
5–87
Stratix II Device Handbook, Volume 1