EP2S90F1020C4N Datasheet, PDF (6/238 Pages) Altera Corporation – The Stratix II family offers the following features

Features
After compilation, check the information messages for a full list of I/O,
DQ, LVDS, and other pins that are not available because of the selected
migration path.
Table 1–4 lists the Stratix II device package offerings and shows the total
number of non-migratable user I/O pins when migrating from one
density device to a larger density device. Additional I/O pins may not be
migratable if migrating from the larger device to the smaller density
device.
1 When moving from one density to a larger density, the larger
density device may have fewer user I/O pins. The larger device
requires more power and ground pins to support the additional
logic within the device. Use the Quartus II Pin Planner to
determine which user I/O pins are migratable between the two
devices.
Table 1–4. Total Number of Non-Migratable I/O Pins for Stratix II Vertical Migration Paths
Vertical Migration
Path
EP2S15 to EP2S30
EP2S15 to EP2S60
EP2S30 to EP2S60
EP2S60 to EP2S90
EP2S60 to EP2S130
EP2S60 to EP2S180
EP2S90 to EP2S130
EP2S90 to EP2S180
EP2S130 to EP2S180
484-Pin
FineLine BGA
0 (1)
8 (1)
8 (1)
672-Pin
FineLine BGA
0
0
8
780-Pin
FineLine BGA
0 (1)
1020-Pin
FineLine BGA
0
0
0
16
16
0
1508-Pin
FineLine BGA
17
0
0
Note to Table 1–4:
(1) Some of the DQ/DQS pins are not migratable. Refer to the Quartus II software information messages for more
detailed information.
f
1 To determine if your user I/O assignments are correct, run the
I/O Assignment Analysis command in the Quartus II software
(Processing > Start > Start I/O Assignment Analysis).
Refer to the I/O Management chapter in volume 2 of the Quartus II
Handbook for more information on pin migration.
1–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007