EP2S90F1020C4N Datasheet, PDF (81/238 Pages) Altera Corporation – The Stratix II family offers the following features

Stratix II Architecture
Figure 2–48. Column I/O Block Connection to the Interconnect Note (1)
32 Data &
Control Signals
from Logic Array (1)
Vertical I/O Block
Vertical I/O
Block Contains
up to Four IOEs
I/O Block
Local Interconnect
32
IO_dataina[3:0]
io_clk[7..0]
IO_datainb[3:0]
R4 & R24
Interconnects
LAB
LAB
LAB
LAB Local
Interconnect
C4 & C16
Interconnects
Note to Figure 2–48:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
Altera Corporation
May 2007
2–73
Stratix II Device Handbook, Volume 1