EP2AGX260EF29I3N Datasheet, PDF (8/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

1–8
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
I/O Pin Leakage Current
Table 1–7 lists the Arria II GX I/O pin leakage current specifications.
Table 1–7. I/O Pin Leakage Current for Arria II GX Devices
Symbol
I_I
I_OZ
Description
Input pin
Tri-stated I/O pin
Conditions
V_I = 0 V to V_CCIOMAX
V_O = 0 V to V_CCIOMAX
Min
Typ
Max Unit
–10
—
10
µA
–10
—
10
µA
Table 1–8 lists the Arria II GZ I/O pin leakage current specifications.
Table 1–8. I/O Pin Leakage Current for Arria II GZ Devices
Symbol
I_I
I_OZ
Description
Input pin
Tri-stated I/O pin
Conditions
V_I = 0 V to V_CCIOMAX
V_O = 0 V to V_CCIOMAX
Min
Typ
Max Unit
–20
—
20
µA
–20
—
20
µA
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 1–9 lists bus hold specifications for Arria II GX devices.
Table 1–9. Bus Hold Parameters for Arria II GX Devices (Note 1)
V_CCIO (V)
Parameter Symbol Cond.
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold
low,
sustaining
I_SUSL
V_IN > V_IL
(max.)
8
—
12
—
30
—
50
— 70 — 70 — µA
current
Bus-hold
high,
sustaining
I_SUSH
V_IN < V_IL
(min.)
–8
—
–12
—
–30
—
–50
— –70 — –70 — µA
current
Bus-hold
low,
overdrive
current
I_ODL
0 V < V_IN <
V_CCIO
—
125
—
175
—
200
—
300 — 500 — 500 µA
Bus-hold
high,
overdrive
current
I_ODH
0 V < V_IN <
V_CCIO
—
–125
—
–175
—
–200
—
–300 — –500 — –500 µA
Bus-hold
trip point
V_TRIP
—
0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V
Note to Table 1–9:
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation