EP2AGX260EF29I3N Datasheet, PDF (66/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

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Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 3 of 3)
Symbol
Conditions
C3, I3
C4, I4
Unit
Min
Typ
Max
Min
Typ
Max
t_{RISE &} t_FALL
TCCS
True differential I/O
standards
—
—
200
—
—
200
ps
Emulated differential
I/O standards with
three external output
—
—
250
—
—
300
ps
resistor networks
Emulated differential
I/O standards with
one external output
—
—
500
—
—
500
ps
resistor
True LVDS
—
—
100
—
—
100
ps
Emulated
LVDS_E_3R
—
—
250
—
—
250
ps
Receiver
True differential I/O
standards - f_HSDRDPA
(data rate)
SERDES factor
J = 3 to 10
150
—
1250
150
—
1250 Mbps
SERDES factor
J = 3 to 10
(4)
—
(6)
(4)
—
(6)
Mbps
f_HSDR (data rate)
SERDES factor J = 2,
uses DDR registers
(4)
—
(5)
(4)
—
(5)
Mbps
SERDES factor J = 1,
uses an SDR register
(4)
—
(5)
(4)
—
(5)
Mbps
DPA run length
DPA mode
—
—
10000
—
—
10000
UI
Soft-CDR PPM
tolerance
Soft-CDR mode
—
—
300
—
—
300 ± PPM
Sampling Window
(SW)
Non-DPA mode
—
—
300
—
—
300
ps
Notes to Table 1–54:
(1) When J = 3 to 10, use the SERDES block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(5) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(9) This only applies to DPA and soft-CDR modes.
(10) This only applies to LVDS source synchronous mode.
Table 1–55 lists DPA lock time specifications for Arria II GX and GZ devices.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation