EP2AGX260EF29I3N Datasheet, PDF (65/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
1–65
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 2 of 3)
Symbol
Conditions
C3, I3
Min
Typ
Max
C4, I4
Min
Typ
Max
f_{HSCLK_OUT} (output
clock frequency)
—
5
—
717 (7)
5
— 717 (7)
Transmitter
SERDES factor, J = 3
to 10
(using dedicated
(4)
—
SERDES) (8)
f_HSDR (true LVDS
output data rate)
SERDES factor J = 2,
(using DDR registers)
(4)
—
SERDES factor J = 1,
(uses an SDR
(4)
—
register)
f_HSDR (emulated
LVDS_E_3R output
(4)
—
data rate) (5)
SERDES factor J = 4
f_HSDR (emulated
LVDS_E_1R output
to 10
(4)
—
data rate)
t_{x Jitter}
Total jitter for data
rate, 600 Mbps to
—
—
1.6 Gbps
Total jitter for data
rate, < 600 Mbps
—
—
t_{x Jitter} - emulated
differential I/O
Total jitter for data
rate, 600 Mbps to
—
—
standards with three
1.25 Gbps
external output resistor
network
Total jitter for data
rate < 600 Mbps
—
—
t_{x Jitter} - emulated
differential I/O
standards with one
—
external output resistor
network
—
—
TX output clock duty
cycle for both True
t_DUTY
and emulated
45
50
differential I/O
standards
1250
(5)
(5)
1152
200
160
0.1
300
0.2
0.15
55
(4)
—
(4)
—
(4)
—
(4)
—
(4)
—
—
—
—
—
—
—
—
—
—
—
45
50
1250
(5)
(5)
800
200
160
0.1
325
0.25
0.15
55
Unit
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
ps
UI
ps
UI
UI
%
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum