EP2AGX260EF29I3N Datasheet, PDF (54/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

1–54
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–44. PLL Specifications for Arria II GX Devices (Part 2 of 3)
Symbol
Description
Min Typ
Max
Unit
Output frequency for internal global or regional clock
(–4 Speed Grade)
—
—
500
MHz
f_OUT
Output frequency for internal global or regional clock
(–5 Speed Grade)
—
—
500
MHz
Output frequency for internal global or regional clock
(–6 Speed Grade)
—
—
400
MHz
Output frequency for external clock output (–4 Speed Grade)
—
—
670 (5)
MHz
f_{OUT_EXT}
Output frequency for external clock output (–5 Speed Grade)
—
—
622 (5)
MHz
Output frequency for external clock output (–6 Speed Grade)
—
—
500 (5)
MHz
t_OUTDUTY Duty cycle for external clock output (when set to 50%)
45
50
t_{OUTPJ_DC}
Dedicated clock output period jitter (f_OUT  100 MHz)
Dedicated clock output period jitter (f_OUT  100 MHz)
—
—
—
—
t_{OUTCCJ_DC}
Dedicated clock output cycle-to-cycle jitter (f_OUT  100 MHz)
Dedicated clock output cycle-to-cycle jitter (f_OUT  100 MHz)
—
—
—
—
f_{OUTPJ_IO}
Regular I/O clock output period jitter (f_OUT  100 MHz)
Regular I/O clock output period jitter (f_OUT  100 MHz)
—
—
—
—
f_{OUTCCJ_IO}
Regular I/O clock output cycle-to-cycle jitter (f_OUT  100 MHz)
Regular I/O clock output cycle-to-cycle jitter (f_OUT  100 MHz)
—
—
—
—
t_CONFIGPLL Time required to reconfigure PLL scan chains
—
3.5
55
%
300
ps (p–p)
30
mUI (p–p)
300
ps (p–p)
30
mUI (p–p)
650
ps (p–p)
65
mUI (p–p)
650
ps (p–p)
65
mUI (p–p)
—
SCANCLK
cycles
t_CONFIGPHASE Time required to reconfigure phase shift
—
1
—
SCANCLK
cycles
f_SCANCLK
t_LOCK
t_DLOCK
SCANCLK frequency
Time required to lock from end of device configuration
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
—
100
MHz
—
—
1
ms
—
—
1
ms
PLL closed-loop low bandwidth
—
0.3
—
MHz
f_{CL B W}
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
—
1.5
—
MHz
—
4
—
MHz
t_{PLL_PSERR}
t_ARESET
Accuracy of PLL phase shift
Minimum pulse width on areset signal
—
—
±50
ps
10
—
—
ns
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation