EP2AGX260EF29I3N Datasheet, PDF (76/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

1–76
Chapter 1: Device Datasheet for Arria II Devices
Glossary
Table 1–68. Glossary (Part 3 of 4)
Letter Subject
Definitions
The period of time during which the data must be valid in order to capture it correctly. The setup
and hold times determine the ideal strobe position within the sampling window:
Timing Diagram
SW (sampling
window)
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver
changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold. This
S
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing:
Single-ended
Voltage
Referenced I/O
Standard
Single-Ended Voltage Referenced I/O Standard
V_CCIO
VOH
V_REF
VIH (AC )
VIH(DC)
VIL (D C)
VIL (AC )
VOL
V_SS
t_C
TCCS
(channel-to-
channel-
skew)
High-speed receiver and transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including t_CO variation and
clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under S in this table).
High-speed I/O block: Duty cycle on the high-speed transmitter output clock.
T
t_DUTY
t_FALL
t_INCCJ
t_{OUTPJ_IO}
t_{OUTPJ_DC}
t_RISE
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on the PLL clock input.
Period jitter on the general purpose I/O driven by a PLL.
Period jitter on the dedicated clock output driven by a PLL.
Signal low-to-high transition time (20-80%).
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation