EP2AGX260EF29I3N Datasheet, PDF (30/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

1–30
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 3 of 5)
Symbol/
Description
Receiver DC Coupling
Support
Differential on-chip
termination resistors
Differential and common
mode return loss
Programmable PPM
detector (9)
Run length
Programmable equalization
t_LTR (10)
t_{LTR_LTD_Manual} (11)
t_{LTD_Manual} (12)
t_{LTD_Auto} (13)
Receiver CDR
3 dB Bandwidth in
lock-to-data (LTD) mode
Conditions
—
85 setting
100 setting
120 setting
150- setting
PCIe (Gen 1 and
Gen 2),
XAUI,
HiGig+,
CEI SR/LR,
SRIO SR/LR,
CPRI LV/HV,
OBSAI,
SATA
–C3 and –I3 (1)
Min Typ
Max
–C4 and –I4
Unit
Min Typ
Max
For more information about receiver DC coupling support, refer to the
“DC-Coupled Links” section in the Transceiver Architecture for Arria II
Devices chapter.
85 ± 20%
85 ± 20%

100 ± 20%
100 ± 20%

120 ± 20%
120 ± 20%

150 ± 20%
150 ± 20%

Compliant
—
—
± 62.5, 100, 125, 200, 250, 300, 500, 1,000
ppm
—
—
—
200
—
—
200
UI
—
—
—
16
—
—
16
dB
—
—
—
75
—
—
75
µs
—
15
—
—
15
—
—
µs
—
—
—
4000
—
—
4000
ns
—
—
—
4000
—
—
4000
ns
PCIe Gen1
2.0 - 3.5
MHz
PCIe Gen2
40 - 65
MHz
(OIF) CEI PHY at
6.375 Gbps
20 - 35
MHz
XAUI
10 - 18
MHz
SRIO 1.25 Gbps
10 - 18
MHz
SRIO 2.5 Gbps
10 - 18
MHz
SRIO 3.125 Gbps
6 - 10
MHz
GIGE
6 - 10
MHz
SONET OC12
3-6
MHz
SONET OC48
14 - 19
MHz
Receiver buffer and CDR
offset cancellation time (per
—
—
channel)
Programmable DC gain
DC Gain Setting = 0 —
DC Gain Setting = 1 —
DC Gain Setting = 2 —
—
17000
—
0
—
—
3
—
—
6
—
—
recon
—
17000 ^fig_
clk
cycles
0
—
dB
3
—
dB
6
—
dB
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation