EP2AGX260EF29I3N Datasheet, PDF (53/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
1–53
Core Performance Specifications for the Arria II Device Family
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), embedded memory, configuration, and JTAG specifications for
Arria II GX and GZ devices.
Clock Tree Specifications
Table 1–42 lists the clock tree specifications for Arria II GX devices.
Table 1–42. Clock Tree Performance for Arria II GX Devices
Clock Network
I3, C4
Performance
C5,I5
GCLK and RCLK
500
500
PCLK
420
350
Unit
C6
400
MHz
280
MHz
Table 1–43 lists the clock tree specifications for Arria II GZ devices.
Table 1–43. Clock Tree Performance for Arria II GZ Devices
Performance
Clock Network
Unit
–C3 and –I3
–C4 and –I4
GCLK and RCLK
700
PCLK
500
500
MHz
450
MHz
PLL Specifications
Table 1–44 lists the PLL specifications for Arria II GX devices.
Table 1–44. PLL Specifications for Arria II GX Devices (Part 1 of 3)
Symbol
f_IN
f_INPFD
f_VCO
f_INDUTY
f_EINDUTY
t_INCCJ (3),
(4)
Description
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–4 Speed Grade)
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–5 Speed Grade)
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–6 Speed Grade)
Input frequency to the PFD
PLL VCO operating Range (2)
Input clock duty cycle
External feedback clock input duty cycle
Input clock cycle-to-cycle jitter (Frequency  100 MHz)
Input clock cycle-to-cycle jitter (Frequency  100 MHz)
Min Typ
Max
Unit
5
—
670 (1)
MHz
5
—
622 (1)
MHz
5
—
500 (1)
MHz
5
—
600 —
40
—
40
—
—
—
—
—
325
1,400
60
60
0.15
±750
MHz
MHz
%
%
UI (p–p)
ps (p–p)
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum