EP2AGX260EF29I3N Datasheet, PDF (58/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

1–58
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–47. DSP Block Performance Specifications for Arria II GZ Devices (Note 1) (Part 2 of 2)
Mode
Resources
Used
Number of
Multipliers
Performance
–3
–4
Double mode
1
440
380
Notes to Table 1–47:
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) Maximum for loopback input registers disabled, Round and Saturation disabled, and pipeline and output registers enabled.
Unit
MHz
Embedded Memory Block Specifications
Table 1–48 lists the embedded memory block specifications for Arria II GX devices.
Table 1–48. Embedded Memory Block Performance Specifications for Arria II GX Devices
Resources Used
Memory
Mode
ALUTs
Embedded
Memory
I3
Memory ^{Single port 64 × 10}
0
Logic
Array
Simple dual-port 32 × 20 single
clock
0
Block
Simple dual-port 64 × 10 single
(MLAB) _clock
0
1
450
1
270
1
428
Single-port 256 × 36
0
1
360
Single-port 256 × 36, with the
read-during-write option set to
0
Old Data
1
250
Simple dual-port 256 × 36 single
CLK
0
1
360
Single-port 256 × 36 single CLK,
M9K
with the read-during-write option
0
Block
set to Old Data
1
250
True dual port 512 × 18 single CLK
0
1
360
True dual-port 512 × 18 single CLK,
with the read-during-write option
0
set to Old Data
1
250
Min Pulse Width (clock high time)
—
—
900
Min Pulse Width (clock low time)
—
—
730
Performance
Unit
C4 C5,I5
C6
500
450
378 MHz
500
450
378 MHz
500
450
378 MHz
400
360
310 MHz
280
250
210 MHz
400
360
310 MHz
280
250
210 MHz
400
360
310 MHz
280
250
210 MHz
850
950
1130
ps
690
770
920
ps
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation