EP2AGX260EF29I3N Datasheet, PDF (55/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
1–55
Table 1–44. PLL Specifications for Arria II GX Devices (Part 3 of 3)
Symbol
Description
Min Typ
Max
Unit
t_{CASC_}
OUTJITTER_
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT  100 MHz)
—
—
425
ps (p-p)
PERIOD_
DEDCLK
(6)_, (7)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT  100 MHz)
—
—
42.5 mUI (p-p)
Notes to Table 1–44:
(1) f_IN is limited by the I/O f_MAX.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f_VCO specification.
(3) A high-input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean-clock source, which is
less than 200 ps.
(4) F_REF is fIN/N when N = 1.
(5) This specification is limited by the lower of the two: I/O f_MAX or f_OUT of the PLL.
(6) Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–62 on page 1–70.
(7) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 Mhz Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
Table 1–45 lists the PLL specifications for Arria II GZ devices when operating in both
the commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (-40° to 100°C).
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 1 of 2)
Symbol
Parameter
Min Typ
Input clock frequency (–3 speed grade)
f_IN
Input clock frequency (–4 speed grade)
5
—
5
—
f_INPFD
f_VCO
Input frequency to the PFD
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
5
—
600 —
600 —
t_EINDUTY
f_OUT
Input clock or external feedback clock input duty cycle
Output frequency for internal global or regional clock
(–3 speed grade)
Output frequency for internal global or regional clock
(–4 speed grade)
40
—
—
—
—
—
f_{OUT_EXT}
Output frequency for external clock output (–3 speed grade) —
—
Output frequency for external clock output (–4 speed grade) —
—
t_OUTDUTY
t_FCOMP
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
45
50
—
—
t_CONFIGPLL
Time required to reconfigure scan chain
— 3.5
t_CONFIGPHASE Time required to reconfigure phase shift
—
1
f_SCANCLK
t_LOCK
scanclk frequency
—
—
Time required to lock from end-of-device configuration or
de-assertion of areset
—
—
Max
717 (1)
717 (1)
325
1,300
1,300
60
700 (2)
500 (2)
717 (2)
717 (2)
55
10
—
—
100
1
Unit
MHz
MHz
MHz
MHz
MHz
%
MHz
MHz
MHz
MHz
%
ns
scanclk
cycles
scanclk
cycles
MHz
ms
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum